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Update for sub-board generation#156

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ducky64 merged 3 commits into
mainfrom
export-tap-consistency
May 18, 2026
Merged

Update for sub-board generation#156
ducky64 merged 3 commits into
mainfrom
export-tap-consistency

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@ducky64 ducky64 commented May 18, 2026

Updates the core HDL library pointer and internals to support the IR changes and multi sub-board netlist generation.

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Pull request overview

Updates EDG-IDE’s Scala-side IR handling to match core HDL library / EDG IR changes and enables writing multiple netlists (one per sub-board path) instead of assuming a single netlist output.

Changes:

  • Update IR pattern matches to accommodate new/changed fields in ExportedExpr and ElaborateRecord.Connect.
  • Write multiple netlist files from the backend result, generating per-sub-board filenames.
  • Replace dependency on BlockConnectivityAnalysis.typeOfPortLike with a local implementation for port-side inference.

Reviewed changes

Copilot reviewed 5 out of 5 changed files in this pull request and generated 5 comments.

File Description
src/main/scala/edg_ide/util/DesignFindDisconnected.scala Updates constraint pattern matching for ExportedExpr to align with IR changes.
src/main/scala/edg_ide/swing/CompilerErrorTreeTableModel.scala Updates Connect record matching for new tap field.
src/main/scala/edg_ide/runner/CompileProcessHandler.scala Writes multiple netlist outputs to disk with derived filenames.
src/main/scala/edg_ide/edgir_graph/ElkEdgirGraphUtils.scala Adjusts port-type extraction logic used for port-side mapping.

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case expr.ValueExpr.Expr.Connected(expr.ConnectedExpr(Some(blockExpr), Some(linkExpr), _, _)) =>
blockExpr.expr
case expr.ValueExpr.Expr.Exported(expr.ExportedExpr(Some(exteriorExpr), Some(interiorExpr), _, _)) =>
case expr.ValueExpr.Expr.Exported(expr.ExportedExpr(Some(exteriorExpr), Some(interiorExpr), false, _, _)) =>
.get
require(netlist.size == 1)

Files.createDirectories(Paths.get(options.netlistFile).getParent)
Comment on lines +435 to +436
val writtenFiles = netlist.map { case (path, netlist) =>
val filename = if (path == DesignPath()) {
Comment on lines +445 to +447
val writer = new FileWriter(filename, StandardCharsets.UTF_8)
writer.write(netlist)
writer.close()
Comment on lines +94 to +98
def typeOfPortLike(portLike: elem.PortLike): ref.LibraryPath = portLike.is match {
case elem.PortLike.Is.LibElem(lib) => lib
case elem.PortLike.Is.Port(port) => port.getSelfClass
case elem.PortLike.Is.Array(port) => port.getSelfClass
case other => throw new IllegalArgumentException(s"Unexpected PortLike ${other.getClass}")
@ducky64 ducky64 merged commit b4073f0 into main May 18, 2026
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@ducky64 ducky64 deleted the export-tap-consistency branch May 18, 2026 00:38
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2 participants