Update for sub-board generation#156
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Pull request overview
Updates EDG-IDE’s Scala-side IR handling to match core HDL library / EDG IR changes and enables writing multiple netlists (one per sub-board path) instead of assuming a single netlist output.
Changes:
- Update IR pattern matches to accommodate new/changed fields in
ExportedExprandElaborateRecord.Connect. - Write multiple netlist files from the backend result, generating per-sub-board filenames.
- Replace dependency on
BlockConnectivityAnalysis.typeOfPortLikewith a local implementation for port-side inference.
Reviewed changes
Copilot reviewed 5 out of 5 changed files in this pull request and generated 5 comments.
| File | Description |
|---|---|
| src/main/scala/edg_ide/util/DesignFindDisconnected.scala | Updates constraint pattern matching for ExportedExpr to align with IR changes. |
| src/main/scala/edg_ide/swing/CompilerErrorTreeTableModel.scala | Updates Connect record matching for new tap field. |
| src/main/scala/edg_ide/runner/CompileProcessHandler.scala | Writes multiple netlist outputs to disk with derived filenames. |
| src/main/scala/edg_ide/edgir_graph/ElkEdgirGraphUtils.scala | Adjusts port-type extraction logic used for port-side mapping. |
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| case expr.ValueExpr.Expr.Connected(expr.ConnectedExpr(Some(blockExpr), Some(linkExpr), _, _)) => | ||
| blockExpr.expr | ||
| case expr.ValueExpr.Expr.Exported(expr.ExportedExpr(Some(exteriorExpr), Some(interiorExpr), _, _)) => | ||
| case expr.ValueExpr.Expr.Exported(expr.ExportedExpr(Some(exteriorExpr), Some(interiorExpr), false, _, _)) => |
| .get | ||
| require(netlist.size == 1) | ||
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| Files.createDirectories(Paths.get(options.netlistFile).getParent) |
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| val writtenFiles = netlist.map { case (path, netlist) => | ||
| val filename = if (path == DesignPath()) { |
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| val writer = new FileWriter(filename, StandardCharsets.UTF_8) | ||
| writer.write(netlist) | ||
| writer.close() |
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| def typeOfPortLike(portLike: elem.PortLike): ref.LibraryPath = portLike.is match { | ||
| case elem.PortLike.Is.LibElem(lib) => lib | ||
| case elem.PortLike.Is.Port(port) => port.getSelfClass | ||
| case elem.PortLike.Is.Array(port) => port.getSelfClass | ||
| case other => throw new IllegalArgumentException(s"Unexpected PortLike ${other.getClass}") |
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Updates the core HDL library pointer and internals to support the IR changes and multi sub-board netlist generation.